 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| K6F2008T2E Family Document Title Preliminary CMOS SRAM www..com 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History 0.0 Initial draft Draft Date June 16 , 2003 Remark Preliminary The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 0.0 June 2003 K6F2008T2E Family 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM FEATURES * Process Technology: Full CMOS * Organization: 256Kx8 * Power Supply Voltage: 2.7 ~ 3.6V * Low Data Retention Voltage: 1.5V(Min) * Three State Outputs * Package Type: 32-TSOP1-0813.4F Preliminary CMOS SRAM www..com GENERAL DESCRIPTION The K6F2008T2E families are fabricated by SAMSUNGs advanced Full CMOS process technology. The families support industrial temperature ranges for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed(ns) Standby (ISB1, Typ) 0.5A2) Operating (ICC1, Max) 3mA PKG Type K6F2008T2E-F Industrial(-40~85C) 2.7~3.6V 551)/70ns 32-TSOP1-0813.4F 1. The parameter is measured with 30pF test load. 2. Typical values are measured at VCC=3.0V, TA=25C and not 100% tested. PIN DESCRIPTION A11 A9 A8 A13 WE CS2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. Address 32-sTSOP Type1-Forward Row select Memory array 1024 rows 256x8 columns I/O1 I/O8 Data cont I/O Circuit Column select Data cont Name Function Name Function Address CS1, CS2 Chip Select Input OE WE Output Enable Write Enable Input I/O1~I/O8 Data Inputs/Outputs Vcc Vss DNU Power Ground Do Not Use CS1 CS2 WE OE A0~A17 Address Inputs Control logic SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 0.0 June 2003 K6F2008T2E Family PRODUCT LIST Industrial Temperature Products(-40~85C) Part Name K6F2008T2E-YF55 K6F2008T2E-YF70 Function 32-sTSOP1-F, 55ns, 3.0V/3.3V, LL 32-sTSOP1-F, 70ns, 3.0V/3.3V, LL Preliminary CMOS SRAM www..com FUNCTIONAL DESCRIPTION CS1 H X1) L L L CS2 X1) L H H H OE X1) X1) H L X 1) WE X1) X1) H H L I/O High-Z High-Z High-Z Dout Din Mode Deselected Deselected Output Disable Read Write Power Standby Standby Active Active Active 1. X means dont care (Must be high or low states) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.5V -0.2 to 4.6V 1.0 -65 to 150 -40 to 85 Unit V V W C C K6F2008T2E-F Remark 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 0.0 June 2003 K6F2008T2E Family RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 2.7 0 2.2 -0.23) Typ. 3.0/3.3 0 - Preliminary CMOS SRAM www..com Max 3.6 0 Vcc+0.22) 0.6 Unit V V V V Note: 1. Industrial Product: TA=-40 to 85C, unless otherwise specified. 2. Overshoot: Vcc+2.0V in case of pulse width20ns. 3. Undershoot: -2.0V in case of pulse width20ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Symbol ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(CMOS) VOL VOH ISB1 Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH IOL=2.1mA IOH =-1.0mA Other inputs=Vss to Vcc 1) CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or 2) 0VCS20.2V CS2 controlled) 2.4 0.5 35 0.4 10 mA V V A VIN=Vss to Vcc CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc Cycle time=1s, 100% duty, IIO=0mA, CS10.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V Test Conditions Min -1 -1 Typ1) Max 1 1 3 Unit A A mA 1. Typical value are measured at VCC=3.0V, TA=25C, and not 100% tested. 4 Revision 0.0 June 2003 K6F2008T2E Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See right): CL=100pF+1TTL CL=30pF+1TTL Preliminary CMOS SRAM www..com VTM3) R12) CL1) R23) 1. Including scope and jig capacitance 2. R1=3070, R2=3150 3. VTM =2.8V AC CHARACTERISTICS(Vcc=2.7~3.6V, TA=-40 to 85C) Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Read Chip Select to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z 1. The parameter is measured with 30pF test load. 55ns1) Max 55 55 25 20 20 20 Min 70 10 5 0 0 10 70 60 0 60 50 0 0 30 0 5 55 10 5 0 0 10 55 45 0 45 40 0 0 25 0 5 70ns Max 70 70 35 25 25 20 - Units tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DATA RETENTION CHARACTERISTICS Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CS1Vcc-0.2V1) Vcc=1.5V, CS1Vcc-0.2V1) Min 1.5 0 tRC Typ 0.22) Max 3.6 2 Unit V A ns See data retention waveform 1. CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or CS20.2V(CS2 controlled). 2. Typical values are measured at TA=25C and not 100% tested. 5 Revision 0.0 June 2003 K6F2008T2E Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address tOH Data Out Previous Data Valid tAA (Address Controlled, CS1=OE=VIL, WE=VIH) Preliminary CMOS SRAM www..com tRC Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE tOH OE tOLZ tLZ Data Valid tOHZ Data out NOTES (READ CYCLE) High-Z 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 0.0 June 2003 K6F2008T2E Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) CS1 tAW CS2 tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4) Preliminary CMOS SRAM www..com TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) CS1 tAW CS2 tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4) Data out High-Z High-Z 7 Revision 0.0 June 2003 K6F2008T2E Family TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) tWC Address tAS(3) CS1 tAW CS2 tCW(2) WE tWP(1) tDW Data in Data Valid tDH tWR(4) Preliminary CMOS SRAM www..com Data out NOTES (WRITE CYCLE) High-Z High-Z 1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. DATA RETENTION WAVE FORM CS1 controlled VCC 2.7V tSDR Data Retention Mode tRDR 2.2V VDR CS1VCC - 0.2V CS1 GND CS2 controlled VCC 2.7V CS2 tSDR Data Retention Mode tRDR VDR CS20.2V 0.4V GND 8 Revision 0.0 June 2003 K6F2008T2E Family PACKAGE DIMENSIONS 32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F) Preliminary CMOS SRAM www..com Units: millimeters(inches) 0.20 0.008 +0.10 -0.05 +0.004 -0.002 13.40 0.20 0.528 0.008 #32 #1 0.10 MAX 0.004 ( 8.40 0.331 MAX 8.00 0.315 0.25 ) 0.010 #17 1.00 0.10 0.039 0.004 +0.10 -0.05 0.006 +0.004 -0.002 0.50 0.0197 #16 0.25 TYP 0.010 11.80 0.10 0.465 0.004 0.15 0.05 0.002 MIN 1.20 0.047 MAX 0~8 0.45~0.75 0.018~0.030 ( 0.50 ) 0.020 9 Revision 0.0 June 2003 |
Price & Availability of K6F2008T2E
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |